A wide variety of electronic communication systems utilize an interface known as a “bursty interface”. A bursty interface is an interface that is generally capable of sending or receiving some amount of data on a periodic basis. During a first interval in such a period, data is usually sent or received at a high data rate. During a second interval within the same period, the interface is generally quiescent, i.e. the interface is not sending or receiving data during this second interval.
Bursty interfaces are commonly used because of the bursty nature of data communicated from one system to another. Bursty interfaces are also commonly used as a mechanism for decoupling the physical sampling of data between two systems that are communicatively coupled to each other. In digital systems, for example, two independent systems are generally operated using two independent clocks. A bursty interface is a practical means to enable the transfer of data between two separately clocked systems because a bursty interface generally provides an elasticity buffering capability.
In the past, a bursty interface was generally designed around a linear memory known as a “first-in-first-out” (FIFO) memory. A FIFO memory generally provides an input port and an output port. In many implementations, the input port and the output port can be independently clocked. For example, an independent clocking mechanism is generally provided for a FIFO input port. Using this independent clocking mechanism, data can be stored in the FIFO memory without regard to any clocking mechanism used to retrieve data from the FIFO. It generally follows that a FIFO memory provides a separate and independent clocking mechanism for data retrieval. The retrieval clocking mechanism can be used without regard to the clock mechanism used to store data in the FIFO memory. This type of structure can be used to support a simplistic mechanism for decoupling the clock signals of two independent data systems.
In a bursty interface, the input port of a FIFO has traditionally been used to receive data during a first interval by means of an input clocking mechanism. The output port of the FIFO can then be used to retrieve data using an independent retrieval clocking mechanism. The retrieval clocking mechanism is also generally used as a basis for manipulating data within the system receiving bursty data. As such, the retrieval clocking mechanism can be considered the operating clock that synchronizes the internal operation of the system receiving such bursty data. Data can then be retrieved from the output port of the FIFO at some convenient rate commensurate with the operation of the system receiving the bursty data. Bursty data can then be stored in the FIFO as it arrives at an independent rate from another system.
Modern computer networking systems are also employing bursty interface structures. For example, one common computer networking system known as System Packet Interface (SPI) comprises a specific implementation of a bursty interface that can be used to transfer data packets from one system element to another. The SPI interface has been defined at various levels (e.g. SPI-3 and SPI-4). SPI-3 and SPI-4 define various aspects of the System Packet Interface including but not limited to transfer speed, packet sizing and burst sizing. One interesting characteristic in any bursty interface used to carry data packets is that of packet alignment to a data burst. For example, the data burst may be used to carry a complete single packet, a portion of a single packet, a complete single packet and a portion of a second packet, two or more complete data packets and portions of two or more data packets. Alignment of a data packet to a data burst is a common issue irrespective of the type of bursty interface used to communicate a data packet from one system to another.
Although a FIFO is a useful building block in the design and implementation of a bursty interface, there are several problems that surface when a bursty interface is used to convey a data packet. One specific problem is that of flow control. When a bursty interface is based on a FIFO, flow control is generally designed to reflect the availability of memory within the FIFO. For example, when a FIFO is filled to a certain capacity, the FIFO may not be able to reliably receive an entire burst of data. Accordingly, a system that is delivering bursty data to a receiving system is directed to hold additional data transfers until the receiving system can retrieve some of the data stored in the FIFO. As the receiving system retrieves data stored in the FIFO, the hold directive can be suspended once the FIFO can again reliably accommodate an additional burst of data. Although such flow control can be used to manage a FIFO-based bursty interface, it is simply not suitable when the data carried by a data burst is packetized. This is because a hold directive can be issued during a data burst, preventing the reception of an entire data burst within a given period of time. If the FIFO cannot reliably accommodate an entire data burst, a receiving system may not be able to properly process a data packet if the data packet is only partially received by the FIFO. This is especially problematic in the event that a data packet needs to be forwarded to another system using a second bursty interface.